ICCAD 2001 - PDF Preprint Papers

ICCAD 2001 International Conference on Computer-Aided Design

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ICCAD
2001
IEEE

272views Hardware» more ICCAD 2001»

NetBench: A Benchmarking Suite for Network Processors

14 years 8 months ago

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— In this study we introduce NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications...

Gokhan Memik, William H. Mangione-Smith, Wendong H...

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Id	Views	Title	Status

1	272	NetBench: A Benchmarking Suite for Network Processors	claim
2	256	An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems	claim
3	217	ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits	claim
4	201	An Integrated Data Path Optimization for Low Power Based on Network Flow Method	claim
5	192	BOOM - A Heuristic Boolean Minimizer	claim
6	185	Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis	claim
7	184	CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors	claim
8	180	On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits	claim
9	167	Energy Efficient Real-Time Scheduling	claim
10	163	Predicting the Performance of Synchronous Discrete Event Simulation Systems	claim
11	153	The Sizing Rules Method for Analog Integrated Circuit Design	claim
12	152	Hybrid Structured Clock Network Construction	claim
13	144	Faster SAT and Smaller BDDs via Common Function Structure	claim
14	143	Transient Power Management Through High Level Synthesis	claim
15	128	An Assembly-Level Execution-Time Model for Pipelined Architectures	claim
16	127	What is the Limit of Energy Saving by Dynamic Voltage Scaling?	claim
17	126	Constraint Satisfaction for Relative Location Assignment and Scheduling	claim
18	124	Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs	claim
19	124	Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation	claim
20	117	Static Scheduling of Multi-Domain Memories For Functional Verification	claim
21	113	Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects	claim
22	113	The Design and Optimization of SOC Test Solutions	claim
23	111	Congestion Aware Layout Driven Logic Synthesis	claim
24	111	A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices	claim
25	109	Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization	claim
26	108	Single-Pass Redundancy Addition and Removal	claim
27	108	Multigrid-Like Technique for Power Grid Analysis	claim
28	108	Placement Driven Retiming with a Coupled Edge Timing Model	claim
29	107	A Convex Programming Approach to Positive Real Rational Approximation	claim
30	107	Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate	claim
31	106	Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation	claim
32	106	System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels	claim
33	106	A Layout-Aware Synthesis Methodology for RF Circuits	claim
34	104	A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells	claim
35	103	Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion	claim
36	103	Interconnect Resource-Aware Placement for Hierarchical FPGAs	claim
37	102	Multilevel Approach to Full-Chip Gridless Routing	claim
38	102	Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing	claim
39	102	Symbolic Algebra and Timing Driven Data-flow Synthesis	claim
40	101	Instruction Generation for Hybrid Reconfigurable Systems	claim
41	100	Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets	claim
42	100	Verification of Integer Multipliers on the Arithmetic Bit Level	claim
43	97	Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement	claim
44	95	Improving Memory Energy Using Access Pattern Classification	claim
45	95	On the Signal Bounding Problem in Timing Analysis	claim
46	94	Induction-Based Gate-Level Verification of Multipliers	claim
47	93	Software-Assisted Cache Replacement Mechanisms for Embedded Systems	claim
48	92	Behavioral Modeling of Analog Circuits by Wavelet Collocation Method	claim
49	91	A System for Synthesizing Optimized FPGA Hardware from MATLAB	claim
50	89	Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering	claim
51	89	Sequential SPFDs	claim
52	86	System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip	claim
53	84	Stars in VCC: Complementing Simulation with Worst-Case Analysis	claim
54	84	Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control	claim
55	84	On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits	claim
56	81	Local Search for Final Placement in VLSI Design	claim
57	80	Efficient Performance Estimation for General Real-Time Task Systems	claim
58	77	Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits	claim
59	77	Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method	claim
60	74	Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect	claim
61	70	Non-linear Quantification Scheduling in Image Computation	claim
62	66	Simulation Approaches for Strongly Coupled Interconnect Systems	claim

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