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ASPDAC
1998
ACM
81views Hardware» more  ASPDAC 1998»
13 years 12 months ago
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
ICFEM
2010
Springer
13 years 6 months ago
A Methodology for Automatic Diagnosability Analysis
We present an algorithm based on temporal-epistemic model checking combined with fault injection to analyse automatically the diagnosability of faults by agents in the system. We d...
Jonathan Ezekiel, Alessio Lomuscio
FPL
2005
Springer
98views Hardware» more  FPL 2005»
14 years 1 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
INFOCOM
2007
IEEE
14 years 2 months ago
Performance Evaluation of Loss Networks via Factor Graphs and the Sum-Product Algorithm
— Loss networks provide a powerful tool for the analysis and design of many communication and networking systems. It is well known that a large number of loss networks have produ...
Jian Ni, Sekhar Tatikonda
PLDI
2011
ACM
12 years 10 months ago
Evaluating value-graph translation validation for LLVM
Translation validators are static analyzers that attempt to verify that program transformations preserve semantics. Normalizing translation validators do so by trying to match the...
Jean-Baptiste Tristan, Paul Govereau, Greg Morrise...