ASPDAC 1998 - PDF Preprint Papers

ASPDAC 1998 Asia and South Pacific Design Automation Conference

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ASPDAC
1998
ACM

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Synthesis of Power Efficient Systems-on-Silicon

14 years 3 months ago

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We developed a new modular synthesis approach for design of low-power core-based data-intensive application-speciﬁc systems on silicon. The power optimization is conducted in th...

Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...

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Id	Views	Title	Status

1	160	Synthesis of Power Efficient Systems-on-Silicon	claim
2	119	Integer Programming Models for Optimization Problems in Test Generation	claim
3	112	Real Time Fault Injection Using Logic Emulators	claim
4	107	VLSI for Multimedia U-NII WLANs	claim
5	105	Techniques for Functional Test Pattern Execution	claim
6	105	CMOS Image Sensors with Video Compression	claim
7	101	An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits	claim
8	97	A Novel Design Assistant for Analog Circuits	claim
9	96	A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm	claim
10	93	Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be Made	claim
11	92	A New Design for Double Edge Triggered Flip-flops	claim
12	91	Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening	claim
13	89	On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design	claim
14	87	Hierarchical LVS Based on Hierarchy Rebuilding	claim
15	86	Parallelization in Co-Compilation for Configurable Accelerators	claim
16	86	Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis	claim
17	81	A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks	claim
18	81	Low Power Realization of FIR Filters Implemented using Distributed Arithmetic	claim
19	80	Air-Pressure-Model-Based Fast Algorithms for General Floorplan	claim
20	79	Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization	claim
21	74	Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines	claim
22	72	A New Multiport Memory for High Performance Parallel Processor System with Shared Memory	claim
23	72	Space- and Time-Efficient BDD Construction via Working Set Control	claim
24	70	FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm	claim
25	67	Heterogeneous BISR-approach using System Level Synthesis Flexibility	claim
26	65	A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction	claim
27	49	Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines	claim

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