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DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ICASSP
2008
IEEE
14 years 2 months ago
Optimized distributed 2D transforms for irregularly sampled sensor network grids using wavelet lifting
We address the design and optimization of an energy-efficient lifting-based 2D transform for wireless sensor networks with irregular spatial sampling. The 2D transform is designe...
Godwin Shen, Antonio Ortega
CC
2004
Springer
14 years 1 months ago
Region-Based Partial Dead Code Elimination on Predicated Code
Abstract. This paper presents the design, implementation and experimental evaluation of a practical region-based partial dead code elimination (PDE) algorithm on predicated code in...
Qiong Cai, Lin Gao 0002, Jingling Xue
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
14 years 28 days ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A robust detailed placement for mixed-size IC designs
— The rapid increase in IC design complexity and wide-spread use of intellectual-property (IP) blocks have made the so-called mixed-size placement a very important topic in recen...
Jason Cong, Min Xie