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ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 6 days ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
FORMATS
2007
Springer
13 years 12 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
ATVA
2006
Springer
123views Hardware» more  ATVA 2006»
13 years 11 months ago
Symmetry Reduction for Probabilistic Model Checking Using Generic Representatives
Generic representatives have been proposed for the effective combination of symmetry reduction and symbolic representation with BDDs in non-probabilistic model checking. This appro...
Alastair F. Donaldson, Alice Miller
DCOSS
2006
Springer
13 years 11 months ago
Agimone: Middleware Support for Seamless Integration of Sensor and IP Networks
The scope of wireless sensor network (WSN) applications has traditionally been restricted by physical sensor coverage and limited computational power. Meanwhile, IP networks like t...
Gregory Hackmann, Chien-Liang Fok, Gruia-Catalin R...
ACSAC
2001
IEEE
13 years 11 months ago
Genoa TIE, Advanced Boundary Controller Experiment
This document describes experimentation performed as part of the Genoa Technology Integration Experiment (TIE). Achieved in two phases, the overarching assertion of the Genoa TIE ...
Eric Monteith