ISCAS 1994 - PDF Preprint Papers

ISCAS 1994 International Symposium on Circuits and Systems

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ISCAS
1994
IEEE

138views Hardware» more ISCAS 1994»

High-Throughput Data Compressor Designs Using Content Addressable Memory

14 years 4 months ago

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This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...

Ren-Yang Yang, Chen-Yi Lee

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Id	Views	Title	Status

1	138	High-Throughput Data Compressor Designs Using Content Addressable Memory	claim
2	131	An Efficient Design Method for Optimal Weighted Median Filtering	claim
3	126	Higher-Order Delta-Sigma Frequency to Digital Conversion	claim
4	124	A Recurrent Neural Network for Solving the Shortest Path Problem	claim
5	124	Efficient Gabor Filter Design Using Rician Output Statistics	claim
6	119	Fast Design Algorithms for FIR Notch Filters	claim
7	117	Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy	claim
8	114	The PBF of One Weight Weighted Median Filters	claim
9	113	Jitter in Ring Oscillators	claim
10	111	Linear Phase Cosine Modulated Maximally Decimated Filter Banks with Perfect Reconstruction	claim
11	110	Sinusoidal Excitation on the Chua's Circuit Simulation of Limit Cycles and Chaos	claim
12	104	A Graph-Theoretic Approach to Clock Skew Optimization	claim
13	104	A Homotopy Continuation Method for Parameter Estimation in MRF Models and Image Restoration	claim
14	104	Stereo Correspondence with Discrete-Time Cellular Neural Networks	claim
15	99	Two-Type-Interlaced Structure and LBR Test Applied to the Conventional Filter Realization	claim
16	99	On Perfect-Reconstruction Allpass-Based Cosine-Modulated IIR Filter Banks	claim
17	96	Analysis and Design of Adaptive Self-Trimming Technique for A/D Converters	claim
18	93	The Dynamic Locking Heuristic - A New Graph Partitioning Algorithm	claim
19	93	An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS Transistors	claim
20	93	Adaptive Video Coding using Mixed-Domain Filter Banks having Optimal-Shaped Subbands	claim
21	92	A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses	claim
22	92	A Two-Stage Neural Network DC Fault Dictionary	claim
23	90	Frequency-Domain Analysis of A/D Converter Nonlinearity	claim
24	90	Fault-Tolerant Linear Convolution using Residue Number Systems	claim
25	87	Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew	claim
26	86	Sign Haar Transform	claim
27	85	A BICMOS Limiting Amplifier for SONET OC-3	claim
28	85	Generalized Linear-Phase Lapped Orthogonal Transforms	claim
29	83	Motion Compensated Video Compression and Dense Motion Field Coding	claim
30	82	Mismatch Effects in Time-Interleaved Oversampling Converters	claim
31	82	Multi-Parameter Homotopy Methods for Finding Periodic Solutions of Nonlinear Circuits	claim
32	81	An Efficient VLSI Implementation of Vector-Radix 2-D DCT using Mesh-Connected 2-D Array	claim
33	80	Arabic Text Recognition Using Neural Networks	claim
34	79	Controlling Chaotic Motions in Chua's Circuit via Tunnels	claim
35	77	Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation	claim
36	76	NEAT: An Object Oriented High-Level Synthesis Interface	claim
37	76	Polarity-Coincidence Filter Banks and Nondestructive Evaluation	claim
38	74	Dynamically-Wiresized Elmore-Based Routing Constructions	claim
39	72	Iterative Signal Extrapolation Algorithms with Wavelets	claim
40	72	Improved Methods for the Design of 1-D and 2-D QMF Banks	claim
41	71	DC Offset Performance of Four LMS Adaptive Algorithms	claim
42	70	MOS Active Attenuators for Analog ICs and their Applications to FInite Gain Amplifiers	claim
43	70	Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits	claim
44	67	Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams	claim
45	66	High Speed FIR-Filter Architectures with Scalable Sample Rates	claim
46	65	Gain Enhancement Technique for High-Speed Switched-Capacitor Circuits	claim
47	63	On the Synchronization of Oscillators Coupled by One Negative Resistor	claim
48	62	Performance Measurements in a Manufacturing Communication System	claim
49	62	Performance of Yamakawa's Chaotic Chips and Chua's Circuits for Secure Communications	claim
50	62	Macromodel Simplification Using Dimensional Analysis	claim
51	61	Conversion Error in D/A Converters Employing Dynamic Element Matching	claim
52	61	A Synthesis Framework Based on Trace and Automata Theory	claim
53	60	Improved Two-Layer Coding Schemes for Motion Picture Sequences	claim
54	60	A Comparison of First and Second Generation Switched-Current Cells	claim
55	60	Low-Voltage Low-Power Fully-Integratable Automatic Gain Controls	claim
56	55	Three-Dimensional Linear Trajectory Filtering Using the DWT and the Mixed-Domain Approach	claim

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