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» A RISC Hardware Platform for Low Power Java
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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 1 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
SI3D
1999
ACM
13 years 11 months ago
Applications of pixel textures in visualization and realistic image synthesis
With fast 3D graphics becoming more and more available even on low end platforms, the focus in developing new graphics hardware is beginning to shift towards higher quality render...
Wolfgang Heidrich, Rüdiger Westermann, Hans-P...
WISEC
2010
ACM
14 years 2 months ago
pBMDS: a behavior-based malware detection system for cellphone devices
Computing environments on cellphones, especially smartphones, are becoming more open and general-purpose, thus they also become attractive targets of malware. Cellphone malware no...
Liang Xie, Xinwen Zhang, Jean-Pierre Seifert, Senc...
MOBISYS
2011
ACM
12 years 10 months ago
Exploiting FM radio data system for adaptive clock calibration in sensor networks
Clock synchronization is critical for Wireless Sensor Networks (WSNs) due to the need of inter-node coordination and collaborative information processing. Although many message pa...
Liqun Li, Guoliang Xing, Limin Sun, Wei Huangfu, R...
VEE
2006
ACM
150views Virtualization» more  VEE 2006»
14 years 29 days ago
Evaluating fragment construction policies for SDT systems
Software Dynamic Translation (SDT) systems have been used for program instrumentation, dynamic optimization, security policy enforcement, intrusion detection, and many other uses....
Jason Hiser, Daniel Williams, Adrian Filipi, Jack ...