ISCA 2008 - PDF Preprint Papers

ISCA 2008 International Symposium on Computer Architecture

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ISCA
2008
IEEE

205views Hardware» more ISCA 2008»

VEAL: Virtualized Execution Accelerator for Loops

14 years 6 months ago

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Performance improvement solely through transistor scaling is becoming more and more difﬁcult, thus it is increasingly common to see domain speciﬁc accelerators used in conjunc...

Nathan Clark, Amir Hormati, Scott A. Mahlke

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Id	Views	Title	Status

1	205	VEAL: Virtualized Execution Accelerator for Loops	claim
2	201	iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures	claim
3	188	MIRA: A Multi-layered On-Chip Interconnect Router Architecture	claim
4	185	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware	claim
5	170	Polymorphic On-Chip Networks	claim
6	165	Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory	claim
7	160	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation	claim
8	154	Rerun: Exploiting Episodes for Lightweight Memory Race Recording	claim
9	150	Fetch-Criticality Reduction through Control Independence	claim
10	148	Atomic Vector Operations on Chip Multiprocessors	claim
11	143	TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory	claim
12	142	Improving NAND Flash Based Disk Caches	claim
13	139	Atom-Aid: Detecting and Surviving Atomicity Violations	claim
14	137	Self-Optimizing Memory Controllers: A Reinforcement Learning Approach	claim
15	136	The Design and Performance of a Bare PC Web Server	claim
16	136	A Randomized Queueless Algorithm for Breadth-First Search	claim
17	135	ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency	claim
18	134	Flexible Decoupled Transactional Memory Support	claim
19	134	Achieving Out-of-Order Performance with Almost In-Order Complexity	claim
20	132	Online Estimation of Architectural Vulnerability Factor for Soft Errors	claim
21	130	Corona: System Implications of Emerging Nanophotonic Technology	claim
22	125	Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support	claim
23	119	Technology-Driven, Highly-Scalable Dragonfly Topology	claim
24	116	3D-Stacked Memory Architectures for Multi-core Processors	claim
25	114	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks	claim
26	113	Running a Quantum Circuit at the Speed of Data	claim
27	113	A Two-Level Load/Store Queue Based on Execution Locality	claim
28	112	Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems	claim
29	109	Flexible Hardware Acceleration for Instruction-Grain Program Monitoring	claim
30	107	Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments	claim
31	105	Intra-disk Parallelism: An Idea Whose Time Has Come	claim
32	101	Scalability in Analyzing the Availability of Large-Scale Networks using Multicast	claim
33	92	Counting Dependence Predictors	claim
34	89	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors	claim

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