157 search results - page 22 / 32 » A Real-Time Parallel Benchmark Suite |
HPCA
2000
IEEE
14 years 1 days ago
2000
IEEE
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
OOPSLA
2010
Springer
13 years 6 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
SPAA
2009
ACM
14 years 4 months ago
2009
ACM
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...
PPOPP
2010
ACM
14 years 5 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
HPCA
1999
IEEE
13 years 12 months ago
1999
IEEE
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...