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TVLSI
2008
78views more  TVLSI 2008»
13 years 7 months ago
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng...
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ERSA
2004
130views Hardware» more  ERSA 2004»
13 years 8 months ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
CF
2005
ACM
13 years 9 months ago
SPANIDS: a scalable network intrusion detection loadbalancer
Network intrusion detection systems (NIDS) are becoming an increasingly important security measure. With rapidly increasing network speeds, the capacity of the NIDS sensor can lim...
Lambert Schaelicke, Kyle Wheeler, Curt Freeland
HPCA
1995
IEEE
13 years 11 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...