26 search results - page 3 / 6 » A Reconfigurable Shared Scan-in Architecture |
ERSA
2010
13 years 5 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
ARC
2010
Springer
13 years 11 months ago
2010
Springer
Abstract. This paper presents a brief tutorial and background on implementing filter banks for spectrum sensing. It discusses the advantages of this approach over standard FFT-base...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
TC
2010
13 years 2 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
IFIP
2000
Springer
13 years 11 months ago
2000
Springer
Design of gracefully degrading systems, where functionality is gradually reduced in the face of faults, has traditionally been a very difficult and error-prone task. General appro...