A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics

Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they deliver versatility at the price of complexity they might not be the most efficient interconnect architecture for every application. In this paper, we propose a lightweight onchip interconnect inspired by the reconfigurable mesh model of computation to create a scalable processor fabric. The interconnect is self-reconfigurable since the processor cores reconfigure their local local switch elements to alter the global network topology at runtime. To demonstrate the efficiency of our approach we study matrix multiplication, a fundamental kernel in a number of applications, on the processor array. We prototype the processor fabric on FPGA technology and analyze the efficiency of our many-core implementation on parallel matrix multiplication as a case study. Results show, that parallel matrix multiplication on our proc...

• Type: Journal
• Year: 2010
• Where: ERSA
• Authors: Heiner Giefers, Marco Platzner
• Keywords: ERSA 2010, Hardware, Interconnect, Interconnect Architecture, Processor Fabric