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MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
13 years 11 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
CGO
2003
IEEE
14 years 23 days ago
Phi-Predication for Light-Weight If-Conversion
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
Weihaw Chuang, Brad Calder, Jeanne Ferrante
DAC
2007
ACM
14 years 8 months ago
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
Abstract. Embedded multimedia systems often run multiple time-constrained applications simultaneously. These systems use multiprocessor systems-on-chip of which it must be guarante...
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corp...
VIS
2007
IEEE
132views Visualization» more  VIS 2007»
14 years 8 months ago
Registration Techniques for Using Imperfect and Partially Calibrated Devices in Planar Multi-Projector Displays
Abstract-- Multi-projector displays today are automatically registered, both geometrically and photometrically, using cameras. Existing registration techniques assume pre-calibrate...
Ezekiel Bhasker, Ray Juang, Aditi Majumder
ENTCS
2002
79views more  ENTCS 2002»
13 years 7 months ago
Debugging and Testing Optimizers through Comparison Checking
We present a novel technique called comparison checking that helps optimizer writers debug optimizers by testing, for given inputs, that the semantics of a program are not changed...
Clara Jaramillo, Rajiv Gupta, Mary Lou Soffa