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TVLSI
2002
102views more  TVLSI 2002»
13 years 7 months ago
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
Ramesh Karri, Kaijie Wu
CC
2010
Springer
155views System Software» more  CC 2010»
14 years 2 months ago
Preference-Guided Register Assignment
Abstract. This paper deals with coalescing in SSA-based register allocation. Current coalescing techniques all require the interference graph to be built. This is generally conside...
Matthias Braun, Christoph Mallon, Sebastian Hack
POPL
2003
ACM
14 years 7 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
ICS
2001
Tsinghua U.
13 years 12 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
CC
2007
Springer
129views System Software» more  CC 2007»
14 years 1 months ago
Extended Linear Scan: An Alternate Foundation for Global Register Allocation
In this paper, we extend past work on Linear Scan register allocation, and propose two Extended Linear Scan (ELS) algorithms that retain the compiletime efficiency of past Linear ...
Vivek Sarkar, Rajkishore Barik