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AIPS
2009
13 years 9 months ago
Flexible Execution of Plans with Choice
Dynamic plan execution strategies allow an autonomous agent to respond to uncertainties while improving robustness and reducing the need for an overly conservative plan. Executive...
Patrick R. Conrad, Julie A. Shah, Brian C. William...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
14 years 1 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
IISWC
2008
IEEE
14 years 2 months ago
Characterizing and improving the performance of Intel Threading Building Blocks
Abstract— The Intel Threading Building Blocks (TBB) runtime library [1] is a popular C++ parallelization environment [2][3] that offers a set of methods and templates for creatin...
Gilberto Contreras, Margaret Martonosi
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
14 years 2 months ago
Compositional, dynamic cache management for embedded chip multiprocessors
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ICS
2001
Tsinghua U.
14 years 13 days ago
Global optimization techniques for automatic parallelization of hybrid applications
This paper presents a novel technique to perform global optimization of communication and preprocessing calls in the presence of array accesses with arbitrary subscripts. Our sche...
Dhruva R. Chakrabarti, Prithviraj Banerjee