162 search results - page 14 / 33 » A Scalable Architecture for Maximizing Concurrency |
SBCCI
2003
ACM
14 years 1 months ago
2003
ACM
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
ASPLOS
2009
ACM
14 years 9 months ago
2009
ACM
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
KBSE
2009
IEEE
14 years 3 months ago
2009
IEEE
—As software projects continue to grow in scale, being able to maximize the work that developers can carry out in parallel as a set of concurrent development tasks, without incur...
POPL
2009
ACM
14 years 3 months ago
2009
ACM
Transactional memory (TM) provides a safer, more modular, and more scalable alternative to traditional lock-based synchronization. Implementing high performance TM systems has rec...