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» A Scalable FPGA-based Multiprocessor
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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ECOOP
2004
Springer
14 years 2 months ago
Transactional Monitors for Concurrent Objects
Transactional monitors are proposed as an alternative to monitors based on mutualexclusion synchronization for object-oriented programming languages. Transactional monitors have e...
Adam Welc, Suresh Jagannathan, Antony L. Hosking
ASPLOS
2009
ACM
14 years 9 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
HPCA
2009
IEEE
14 years 9 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
CGO
2008
IEEE
14 years 3 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...