237 search results - page 44 / 48 » A Scalable FPGA-based Multiprocessor |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
KDD
2009
ACM
14 years 9 months ago
2009
ACM
Spatial classification is the task of learning models to predict class labels based on the features of entities as well as the spatial relationships to other entities and their fe...
IPPS
2008
IEEE
14 years 3 months ago
2008
IEEE
We present SNAP (Small-world Network Analysis and Partitioning), an open-source graph framework for exploratory study and partitioning of large-scale networks. To illustrate the c...
RSP
2007
IEEE
14 years 2 months ago
2007
IEEE
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....