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ICCAD
1993
IEEE
139views Hardware» more  ICCAD 1993»
13 years 11 months ago
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
Ing-Jer Huang, Alvin M. Despain
CC
2003
Springer
14 years 24 days ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
RTAS
2010
IEEE
13 years 6 months ago
Scheduling Suspendable, Pipelined Tasks with Non-Preemptive Sections in Soft Real-Time Multiprocessor Systems
While most prior work on multiprocessor real-time scheduling focuses on independent tasks, dependencies due to non-preemptive sections, suspensions, and pipelinebased precedence c...
Cong Liu, James H. Anderson
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 11 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
CASES
2005
ACM
13 years 9 months ago
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific F...
Laura Pozzi, Paolo Ienne