Sciweavers

1234 search results - page 46 / 247
» A Scheduling and Pipelining Algorithm for Hardware Software ...
Sort
View
148
Voted
FPL
2006
Springer
135views Hardware» more  FPL 2006»
15 years 6 months ago
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
Luis G. Barbero, John S. Thompson
125
Voted
ICASSP
2009
IEEE
15 years 16 days ago
VLSI for 5000-word continuous speech recognition
We have developed a VLSI chip for 5,000 word speakerindependent continuous speech recognition. This chip employs a context-dependent HMM (hidden Markov model) based speech recogni...
Young-kyu Choi, Kisun You, Jungwook Choi, Wonyong ...
114
Voted
LCTRTS
2004
Springer
15 years 8 months ago
Procrastination scheduling in fixed priority real-time systems
Procrastination scheduling has gained importance for energy efficiency due to the rapid increase in the leakage power consumption. Under procrastination scheduling, task executio...
Ravindra Jejurikar, Rajesh K. Gupta
144
Voted
SIGGRAPH
1994
ACM
15 years 6 months ago
Priority rendering with a virtual reality address recalculation pipeline
Virtual reality systems are placing never before seen demands on computer graphics hardware, yet few graphics systems are designed specifically for virtual reality. An address rec...
Matthew Regan, Ronald Pose
116
Voted
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 8 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...