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DATE
2003
IEEE

189views Hardware» more DATE 2003»

Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems

14 years 5 months ago

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We present an integrated approach that provides fault tolerance and dynamic power management for a real-time task executing in an embedded system. Fault tolerance is achieved thro...

Ying Zhang, Krishnendu Chakrabarty

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Id	Views	Title	Status

1	189	Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems	claim
2	186	Formal Methods for Integration of Automotive Software	claim
3	180	Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors	claim
4	176	Hardware/Software Partitioning of Operating Systems	claim
5	159	Model-Order Reduction Based on PRONY's Method	claim
6	154	Packetized On-Chip Interconnect Communication Analysis for MPSoC	claim
7	152	Bluetooth Transceiver Design with VHDL-AMS	claim
8	152	Synthesis of CMOS Analog Cells Using AMIGO	claim
9	151	SPIN: A Scalable, Packet Switched, On-Chip Micro-Network	claim
10	151	Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits	claim
11	145	Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair	claim
12	145	Automated Bus Generation for Multiprocessor SoC Design	claim
13	141	On-chip Stack Based Memory Organization for Low Power Embedded Architectures	claim
14	140	Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard	claim
15	138	Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric	claim
16	137	Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs	claim
17	135	Estimation of Bus Performance for a Tuplespace in an Embedded Architecture	claim
18	135	Creating Value Through Test	claim
19	134	A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration	claim
20	133	A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices	claim
21	132	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design	claim
22	132	Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated	claim
23	131	High Speed and Highly Testable Parallel Two-Rail Code Checker	claim
24	130	A Technique for High Ratio LZW Compression	claim
25	130	Automatic Behavioural Model Calibration for Efficient PLL System Verification	claim
26	130	Noise Macromodel for Radio Frequency Integrated Circuits	claim
27	129	A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems	claim
28	128	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation	claim
29	128	Virtual Compression through Test Vector Stitching for Scan Based Designs	claim
30	127	Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology	claim
31	124	Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration	claim
32	124	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs	claim
33	123	RTOS Modeling for System Level Design	claim
34	123	XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines	claim
35	123	Parallel Processing Architectures for Reconfigurable Systems	claim
36	122	Synthesis of Complex Control Structures from Behavioral SystemC Models	claim
37	122	A General Framework for Analysing System Properties in Platform-Based Embedded System Designs	claim
38	120	SystemC-VHDL Co-Simulation and Synthesis in the HW Domain	claim
39	120	Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step	claim
40	120	Crosstalk Reduction in Area Routing	claim
41	119	IPSIM: SystemC 3.0 Enhancements for Communication Refinement	claim
42	119	Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device	claim
43	118	Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints	claim
44	118	Multi-Granularity Metrics for the Era of Strongly Personalized SOCs	claim
45	117	Exploring SW Performance Using SoC Transaction-Level Modeling	claim
46	116	Statistical Timing Analysis Using Bounds	claim
47	116	An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries	claim
48	116	Development and Application of Design Transformations in ForSyDe	claim
49	115	Control Flow Driven Splitting of Loop Nests at the Source Code Level	claim
50	115	Embedded Software in Digital AM-FM Chipset	claim
51	114	Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering	claim
52	114	Software Streaming via Block Streaming	claim
53	114	Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts	claim
54	114	A New Approach to Test Generation and Test Compaction for Scan Circuits	claim
55	113	Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform	claim
56	112	Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0	claim
57	112	Automatic Generation of Simulation Monitors from Quantitative Constraint Formula	claim
58	112	Safe Automotive Software Development	claim
59	109	Fully Automatic Test Program Generation for Microprocessor Cores	claim
60	109	A Novel Metric for Interconnect Architecture Performance	claim
61	109	Run-Time Management of Logic Resources on Reconfigurable Systems	claim
62	109	Data Space Oriented Scheduling in Embedded Systems	claim
63	109	A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors	claim
64	108	System-Level Power Analysis Methodology Applied to the AMBA AHB Bus	claim
65	108	Generalized Posynomial Performance Modeling	claim
66	108	Comparing Analytical Modeling with Simulation for Network Processors: A Case Study	claim
67	108	EBIST: A Novel Test Generator with Built-In Fault Detection Capability	claim
68	108	HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder	claim
69	106	Reconfigurable Signal Processing in Wireless Terminals	claim
70	105	Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation	claim
71	105	Approximation Approach for Timing Jitter Characterization in Circuit Simulators	claim
72	105	Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results	claim
73	104	A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories	claim
74	104	Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip	claim
75	104	Symbolic Analysis of Nonlinear Analog Circuits	claim
76	103	Area Fill Generation With Inherent Data Volume Reduction	claim
77	103	Verification of the RF Subsystem within Wireless LAN System Level Simulation	claim
78	103	Reduced Delay Uncertainty in High Performance Clock Distribution Networks	claim
79	102	G-MAC: An Application-Specific MAC/Co-Processor Synthesizer	claim
80	102	Power Constrained High-Level Synthesis of Battery Powered Digital Systems	claim
81	102	Non-Enumerative Path Delay Fault Diagnosis	claim
82	101	Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures	claim
83	101	Energy Estimation for Extensible Processors	claim
84	101	Combined FDTD/Macromodel Simulation of Interconnected Digital Devices	claim
85	101	Introduction to Hardware Abstraction Layers for SoC	claim
86	101	On Modeling Cross-Talk Faults	claim
87	100	Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals	claim
88	100	Dynamic Tool Integration in Heterogeneous Computer Networks	claim
89	99	RF-BIST: Loopback Spectral Signature Analysis	claim
90	99	Load Distribution with the Proximity Congestion Awareness in a Network on Chip	claim
91	99	Set Top Box SoC Design Methodology at STMicroelectronics	claim
92	99	Instruction Set Emulation for Rapid Prototyping of SoCs	claim
93	99	Software Architectural Transformations: A New Approach to Low Energy Embedded Software	claim
94	99	Fast Computation of Data Correlation Using BDDs	claim
95	98	Verification of a Complex SoC: The PRO3 Case-Study	claim
96	98	Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs	claim
97	98	On the Characterization of Hard-to-Detect Bridging Faults	claim
98	98	Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol	claim
99	97	Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units	claim
100	97	Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation	claim
101	96	Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems	claim
102	96	Time Domain Multiplexed TAM: Implementation and Comparison	claim
103	96	Test Data Compression: The System Integrator's Perspective	claim
104	96	A System to Validate and Certify Soft and Hard IP	claim
105	96	Power/Ground Mesh Area Optimization Using Multigrid-Based Technique	claim
106	95	A New Simulation Technique for Periodic Small-Signal Analysis	claim
107	95	Compiler Support for Reducing Leakage Energy Consumption	claim
108	94	A Lightweight Approach for Embedded Reconfiguration of FPGAs	claim
109	94	Platform-Based Testbench Generation	claim
110	94	Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors	claim
111	94	SystemC-AMS Requirements, Design Objectives and Rationale	claim
112	94	Profile-Driven Selective Code Compression	claim
113	93	Decomposition of Extended Finite State Machine for Low Power Design	claim
114	93	Comparison of Test Pattern Decompression Techniques	claim
115	93	Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip	claim
116	93	Timing Verification with Crosstalk for Transparently Latched Circuits	claim
117	92	An Integrated Approach for Improving Cache Behavior	claim
118	92	Local Search for Boolean Relations on the Basis of Unit Propagation	claim
119	92	A Low Device Occupation IP to Implement Rijndael Algorithm	claim
120	91	Multithreaded Synchronous Data Flow Simulation	claim
121	91	Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs	claim
122	90	Extending JTAG for Testing Signal Integrity in SoCs	claim
123	90	Interactive Ray Tracing on Reconfigurable SIMD MorphoSys	claim
124	90	Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems	claim
125	90	Mapping Applications to an FPFA Tile	claim
126	90	Online Scheduling for Block-Partitioned Reconfigurable Devices	claim
127	90	Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching	claim
128	89	A New Crosstalk Noise Model for DOMINO Logic Circuits	claim
129	89	Heterogeneous Programmable Logic Block Architectures	claim
130	88	Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues	claim
131	87	A Proposal for Transaction-Level Verification with Component Wrapper Language	claim
132	87	A First Step Towards Hw/Sw Partitioning of UML Specifications	claim
133	87	FPGA-Based Implementation of a Serial RSA Processor	claim
134	87	A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification	claim
135	86	Layered, Multi-Threaded, High-Level Performance Design	claim
136	86	Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions	claim
137	86	PLFire: A Visualization Tool for Asynchronous Phased Logic Designs	claim
138	86	Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects	claim
139	86	A Top-Down Microsystems Design Methodology and Associated Challenges	claim
140	86	Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems	claim
141	85	Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface	claim
142	85	Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis	claim
143	84	PARLAK: Parametrized Lock Cache Generator	claim
144	84	Micro-Network for SoC: Implementation of a 32-Port SPIN network	claim
145	84	Interconnect Planning with Local Area Constrained Retiming	claim
146	84	Dynamic Functional Unit Assignment for Low Power	claim
147	84	SoC Design and Test Considerations	claim
148	83	On-Chip Stochastic Communication	claim
149	82	Scaling into Ambient Intelligence	claim
150	82	A Circuit SAT Solver With Signal Correlation Guided Learning	claim
151	82	A Solution for Hardware Emulation of Non Volatile Memory Macrocells	claim
152	81	Figure of Merit Based Selection of A/D Converters	claim
153	81	Linear Model-Based Error Identification and Calibration for Data Converters	claim
154	81	Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations	claim
155	80	Verification of Proofs of Unsatisfiability for CNF Formulas	claim
156	80	Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy	claim
157	80	Consequences of RAM Bitline Twisting for Test Coverage	claim
158	79	Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design	claim
159	79	High-Level Allocation to Minimize Internal Hardware Wastage	claim
160	79	Time Budgeting in a Wireplanning Context	claim
161	78	From C Programs to the Configure-Execute Model	claim
162	78	An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor	claim
163	77	Mesh Partitioning Approach to Energy Efficient Data Layout	claim
164	77	Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST	claim
165	77	Formal Semantics of Synchronous SystemC	claim
166	76	Library Functions Timing Characterization for Source-Level Analysis	claim
167	76	Modeling Noise Transfer Characteristic of Dynamic Logic Gates	claim
168	76	A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization	claim
169	76	Modeling and Evaluation of Substrate Noise Induced by Interconnects	claim
170	75	Circuit and Platform Design Challenges in Technologies beyond 90nm	claim
171	75	SAT-Based Techniques in System Synthesis	claim
172	75	Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures	claim
173	75	Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes	claim
174	73	Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG	claim
175	72	Processor/Memory Co-Exploration on Multiple Abstraction Levels	claim
176	72	Network Processing Challenges and an Experimental NPU Platform	claim
177	70	Runtime Code Parallelization for On-Chip Multiprocessors	claim
178	70	A Fast Algorithm for the Layout Based Electro-Thermal Simulation	claim
179	69	Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling	claim
180	69	Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information	claim
181	67	Refinement of Mixed-Signal Systems with SystemC	claim
182	66	Using RTL Statespace Information and State Encoding for Induction Based Property Checking	claim
183	65	Masking the Energy Behavior of DES Encryption	claim
184	64	Improving the Efficiency of Memory Partitioning by Address Clustering	claim
185	63	NPSE: A High Performance Network Packet Search Engine	claim
186	62	RTL Test Pattern Generation for High Quality Loosely Deterministic BIST	claim
187	61	Reducing Multi-Valued Algebraic Operations to Binary	claim
188	59	Hardware/Software Design Space Exploration for a Reconfigurable Processor	claim
189	46	Combination of Lower Bounds in Exact BDD Minimization	claim

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