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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 1 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee
ISORC
2005
IEEE
14 years 1 months ago
Stochastic, Utility Accrual Real-Time Scheduling with Task-Level and System-Level Timeliness Assurances
Heuristic algorithms have enjoyed increasing interests and success in the context of Utility Accrual (UA) scheduling. However, few analytical results, such as bounds on task-level...
Peng Li, Hyeonjoong Cho, Binoy Ravindran, E. Dougl...
ICONS
2008
IEEE
14 years 2 months ago
An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three
DL systems with bilinear structure recently became an important base for cryptographic protocols such as identity-based encryption (IBE). Since the main computational task is the ...
Giray Kömürcü, Erkay Savas
SAC
2006
ACM
14 years 2 months ago
Event-driven scheduling for dynamic workload scaling in uniprocessor embedded systems
Many embedded systems are designed to take timely reactions to the occurrences of interested scenarios. Sometimes transient overloads might be experienced due to hardware malfunct...
Li-Pin Chang
IPPS
2006
IEEE
14 years 2 months ago
Schedulability analysis of AR-TP, a Ravenscar compliant communication protocol for high-integrity distributed systems
A new token-passing algorithm called AR-TP for avoiding the non-determinism of some networking technologies is presented. This protocol allows the schedulability analysis of the n...
Santiago Urueña, Juan Zamorano, Daniel Berj...