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GECCO
2005
Springer
232views Optimization» more  GECCO 2005»
14 years 1 months ago
A hardware pipeline for function optimization using genetic algorithms
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...
Malay Kumar Pakhira, Rajat K. De
CODES
2002
IEEE
14 years 15 days ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
14 years 14 days ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
IPPS
1998
IEEE
13 years 11 months ago
Predicated Software Pipelining Technique for Loops with Conditions
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
Dragan Milicev, Zoran Jovanovic