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INTEGRATION
2008
127views more  INTEGRATION 2008»
13 years 6 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
14 years 1 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles
FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
13 years 11 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki
FPGA
2009
ACM
233views FPGA» more  FPGA 2009»
14 years 2 months ago
FPCNA: a field programmable carbon nanotube array
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...
Chen Dong, Scott Chilstedt, Deming Chen
FCCM
2005
IEEE
123views VLSI» more  FCCM 2005»
14 years 1 months ago
A Novel 2D Filter Design Methodology for Heterogeneous Devices
In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal ...
Christos-Savvas Bouganis, George A. Constantinides...