A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse.

• Type: Journal
• Year: 2008
• Where: INTEGRATION
• Authors: Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni
• Keywords: Field Programmable Gate Array, INTEGRATION 2006, INTEGRATION 2008, Programmable Data Transmission, Viterbi Decoder