Sciweavers

210 search results - page 29 / 42
» A Self-Reconfigurable Gate Array Architecture
Sort
View
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
13 years 11 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski
ARVLSI
1995
IEEE
78views VLSI» more  ARVLSI 1995»
13 years 11 months ago
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Sch...
ANCS
2005
ACM
14 years 1 months ago
High-throughput linked-pattern matching for intrusion detection systems
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented....
Zachary K. Baker, Viktor K. Prasanna
FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
14 years 1 months ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
13 years 11 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...