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» A Self-Reconfigurable Gate Array Architecture
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129
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HPCA
1998
IEEE
15 years 8 months ago
FPGA Based Custom Computing Machines for Irregular Problems
Over the past few years there has been increased interest in building custom computing machines (CCMs) as a way of achieving very high performance on specific problems. The advent...
David Abramson, Paul Logothetis, Adam Postula, Mar...
104
Voted
DAC
2005
ACM
15 years 5 months ago
Design methodology for IC manufacturability based on regular logic-bricks
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and de...
V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani,...
135
Voted
TAMC
2007
Springer
15 years 9 months ago
Improving the Average Delay of Sorting
In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the ...
Andreas Jakoby, Maciej Liskiewicz, Rüdiger Re...
141
Voted
CODES
2007
IEEE
15 years 10 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
119
Voted
IPPS
2009
IEEE
15 years 10 months ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...