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» A Self-Tuning Configurable Cache
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ICIP
2010
IEEE
13 years 4 months ago
Rate-distortion based reconstruction optimization in distributed source coding for interactive multiview video streaming
Interactive multiview video streaming (IMVS) is an application where, as the streaming multiview video is played back in time, an observer iteratively requests one of many availab...
Ngai-Man Cheung, Antonio Ortega, Gene Cheung
ICS
2001
Tsinghua U.
13 years 11 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 1 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ASPLOS
2008
ACM
13 years 8 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
13 years 11 months ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid