Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu,...
Abstract-- In this paper a novel pulse sequence testing methodology is presented [22] as an alternative to Time Domain Reflectometry (TDR) for transmission line health condition mo...
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
Abstract--In this paper, we report some results on hardware and software co-design of an adaptive linear neuron (ADALINE) based control system. A discrete-time Proportional-Integra...