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» A Simple Proof Technique for Certain Parametricity Results
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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
GECCO
2007
Springer
192views Optimization» more  GECCO 2007»
14 years 1 months ago
On the runtime analysis of the 1-ANT ACO algorithm
The runtime analysis of randomized search heuristics is a growing field where, in the last two decades, many rigorous results have been obtained. These results, however, apply pa...
Benjamin Doerr, Frank Neumann, Dirk Sudholt, Carst...
ICAC
2005
IEEE
14 years 1 months ago
Decentralised Autonomic Computing: Analysing Self-Organising Emergent Behaviour using Advanced Numerical Methods
When designing decentralised autonomic computing systems, a fundamental engineering issue is to assess systemwide behaviour. Such decentralised systems are characterised by the la...
Tom De Wolf, Giovanni Samaey, Tom Holvoet, Dirk Ro...
CORR
2004
Springer
177views Education» more  CORR 2004»
13 years 7 months ago
Typestate Checking and Regular Graph Constraints
We introduce regular graph constraints and explore their decidability properties. The motivation for regular graph constraints is 1) type checking of changing types of objects in ...
Viktor Kuncak, Martin C. Rinard
CODES
2004
IEEE
13 years 11 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...