1065 search results - page 2 / 213 » A Simulation Based Study of TLB Performance |
WSC
1997
13 years 9 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
IRI
2009
IEEE
14 years 2 months ago
2009
IEEE
A 4KB page size has been used for Virtual Memory since the sixties. In fact, today, the most common page size is still 4KB. Choosing a page size is finding the middle ground betwe...
SIGMETRICS
2003
ACM
14 years 26 days ago
2003
ACM
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
GLOBECOM
2009
IEEE
14 years 2 months ago
2009
IEEE
— Recently, there has been an increasing interest in developing 60 GHz wireless personal area networks (WPANs) for short-range high-speed wireless communications. Both industrial...
ANTSW
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. We study through simulation the performance of two MANET routing algorithms in a realistic urban environment. The two algorithms, AODV and AntHocNet, are representative o...