Effect of node size on the performance of cache-conscious B+-trees

In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance by reducing the number of processor cache misses that are incurred during a search operation. Conventional wisdom suggests that the index’s node size should be equal to the cache line size in order to minimize the number of cache misses and improve performance. As we show in this paper, this design choice ignores additional effects, such as the number of instructions executed and the number of TLB misses, which play a significant role in determining the overall performance. To capture the impact of node size on the performance of a cache-conscious B+-tree (CSB+-tree), we first develop an analytical model based on the fundamental components of the search process. This model is then validated with an actual implementation, demonstrating that the model is accurate. Both the analytical model and experiments co...

• Type: Conference
• Year: 2003
• Where: SIGMETRICS
• Authors: Richard A. Hankins, Jignesh M. Patel
• Keywords: Cache Line Size, Cache Misses, Processor Cache Misses, SIGMETRICS 2003