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ICPADS
2006
IEEE
14 years 2 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
14 years 2 months ago
A novel Fisher discriminant for biometrics recognition: 2DPCA plus 2DFLD
— this paper presents a novel image feature extraction and recognition method two dimensional linear discriminant analysis (2DLDA) in a much smaller subspace. Image representatio...
R. M. Mutelo, Li Chin Khor, Wai Lok Woo, Satnam Si...
ISCC
2006
IEEE
154views Communications» more  ISCC 2006»
14 years 2 months ago
Decentralized Load Balancing for Highly Irregular Search Problems
In this paper, we present a Dynamic Load Balancing (DLB) policy for problems characterized by a highly irregular search tree, whereby no reliable workload prediction is available....
Giuseppe Di Fatta, Michael R. Berthold
CASES
2006
ACM
14 years 2 months ago
High-level languages for small devices: a case study
In this paper we study, through a concrete case, the feasibility of using a high-level, general-purpose logic language in the design and implementation of applications targeting w...
Manuel Carro, José F. Morales, Henk L. Mull...
CASES
2006
ACM
14 years 2 months ago
A dynamic binary instrumentation engine for the ARM architecture
Dynamic binary instrumentation (DBI) is a powerful technique for analyzing the runtime behavior of software. While numerous DBI frameworks have been developed for general-purpose ...
Kim M. Hazelwood, Artur Klauser