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» A Spatial Logic for Concurrency
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IOLTS
2003
IEEE
126views Hardware» more  IOLTS 2003»
14 years 29 days ago
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...
IPPS
1997
IEEE
13 years 12 months ago
Optimization Schemas for Parallel Implementation of Nondeterministic Languages and Systems
Naive parallel implementation of nondeterministic systems (such as a theorem proving system) and languages (such as a logic, constraint, or a concurrent constraint language)can re...
Gopal Gupta, Enrico Pontelli
APAL
2008
80views more  APAL 2008»
13 years 7 months ago
System BV is NP-complete
System BV is an extension of multiplicative linear logic (MLL) with the rules mix, nullary mix, and a self-dual, non-commutative logical operator, called seq. While the rules mix ...
Ozan Kahramanogullari
DAC
2005
ACM
14 years 8 months ago
A lattice-based framework for the classification and design of asynchronous pipelines
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Peggy B. McGee, Steven M. Nowick
ECMAST
1997
Springer
74views Multimedia» more  ECMAST 1997»
13 years 12 months ago
Object Encapsulation of Multiscale Image Region Representations
: This paper attempts to evaluate quantitatively the performance trade-offs involved in applying object-oriented software methodologies to region-based representations of images an...
Marc Brelot, Gilles Privat