340 search results - page 8 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
DFT
1997
IEEE
14 years 2 months ago
1997
IEEE
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
ISPD
2005
ACM
14 years 3 months ago
2005
ACM
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
ETS
2006
IEEE
14 years 3 months ago
2006
IEEE
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...