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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
Cache aware compression for processor debug support
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
LCPC
2001
Springer
13 years 12 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann
DCC
2002
IEEE
14 years 7 months ago
Compression Techniques for Active Video Content
Conventional digital video playback systems provide only limited user interactivity, mostly in the form of VCRlike controls such as fast forward/backward, slow motion, pause/stop,...
Anindya Neogi, Tzi-cker Chiueh
CORR
2000
Springer
230views Education» more  CORR 2000»
13 years 7 months ago
Integrating E-Commerce and Data Mining: Architecture and Challenges
We show that the e-commerce domain can provide all the right ingredients for successful data mining. We describe an integrated architecture for supporting this integration. The ar...
Suhail Ansari, Ron Kohavi, Llew Mason, Zijian Zhen...
CGO
2006
IEEE
14 years 1 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal