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INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
CAV
2008
Springer
131views Hardware» more  CAV 2008»
13 years 9 months ago
Validating High-Level Synthesis
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
ICIP
2010
IEEE
13 years 5 months ago
Stochastic gradient descent for robust inverse photomask synthesis in optical lithography
Optical lithography is a critical step in the semiconductor manufacturing process, and one key problem is the design of the photomask for a particular circuit pattern, given the o...
Ningning Jia, Edmund Y. Lam
ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
14 years 4 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 1 months ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...