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» A Systematic Approach for Designing Testable VLSI Circuits
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DFT
1997
IEEE
93views VLSI» more  DFT 1997»
13 years 12 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
DAC
2012
ACM
11 years 10 months ago
Process variation in near-threshold wide SIMD architectures
Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and par...
Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongj...
VLSID
1999
IEEE
111views VLSI» more  VLSID 1999»
14 years 6 hour ago
A New Approach for CMOS Op-Amp Synthesis
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...
Pradip Mandal, V. Visvanathan
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 2 months ago
A Generic Standard Cell Design Methodology for Differential Circuit Styles
In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a syst...
Stéphane Badel, Erdem Guleyupoglu, Ozgur In...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 19 days ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng