209 search results - page 26 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
ISPD
2012
ACM
12 years 3 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
VLSI
2010
Springer
13 years 6 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
DFT
2002
IEEE
14 years 21 days ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...