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» A Systematic Approach for Designing Testable VLSI Circuits
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EUROCAST
2001
Springer
106views Hardware» more  EUROCAST 2001»
14 years 6 days ago
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata
CAST.FSM denotes a CAST tool which has been developed at the Institute of Systems Science at the University of Linz during the years 1986-1993. The first version of CAST.FSM was i...
Michael Affenzeller, Franz Pichler, Rudolf Mittelm...
FPL
2001
Springer
130views Hardware» more  FPL 2001»
14 years 6 days ago
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebau...
GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar
CLEIEJ
2010
13 years 5 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
VLSID
2000
IEEE
95views VLSI» more  VLSID 2000»
14 years 2 days ago
Hierarchical Error Diagnosis Targeting RTL Circuits
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee...