Sciweavers

452 search results - page 84 / 91
» A Systematic Process to Design Product Line Architecture
Sort
View
OIR
2007
123views more  OIR 2007»
13 years 7 months ago
The IP's guide to the galaxy of portal planning: part III - administrative framework
Purpose – This article is the third in a four-part series that aims to illustrate the process involved in planning a portal and creating a portal definition document. Design/me...
Amy M. Finley, Rebecca H. Augustyniak
SOSP
2009
ACM
14 years 4 months ago
Helios: heterogeneous multiprocessing with satellite kernels
Helios is an operating system designed to simplify the task of writing, deploying, and tuning applications for heterogeneous platforms. Helios introduces satellite kernels, which ...
Edmund B. Nightingale, Orion Hodson, Ross McIlroy,...
PDP
2010
IEEE
14 years 3 days ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ICS
2001
Tsinghua U.
14 years 6 days ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
SEUS
2008
IEEE
14 years 2 months ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic