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IEEEPACT
2005
IEEE
14 years 1 months ago
Communication Optimizations for Fine-Grained UPC Applications
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...
Wei-Yu Chen, Costin Iancu, Katherine A. Yelick
PPOPP
2006
ACM
14 years 1 months ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 7 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 2 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
HPCA
2002
IEEE
14 years 25 days ago
User-Level Communication in Cluster-Based Servers
Clusters of commodity computers are currently being used to provide the scalability required by severalpopular Internet services. In this paper we evaluate an efficient cluster-b...
Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ric...