1860 search results - page 304 / 372 » A Temporal Logic of Robustness |
CAV
2001
Springer
14 years 1 months ago
2001
Springer
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
DSN
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper describes an experiment in formal specification and validation performed in the context of an industrial joint project. The project involved an Italian company working...
ISSTA
2000
ACM
14 years 1 months ago
2000
ACM
—Network protocols are often analyzed using simulations. We demonstrate how to extend such simulations to check propositions expressing safety properties of network event traces ...
AMAST
2000
Springer
14 years 1 months ago
2000
Springer
Abstract. Algebraic compilers provide a powerful and convenient mechanism for specifying language translators. With each source language operation one associates a computation for ...