295 search results - page 4 / 59 » A Test Generation Strategy for Pairwise Testing |
COMPSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Combinatorial covering arrays have been used in several testing approaches. This paper first discusses some existing methods for finding such arrays. Then a SAT-based approach a...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICMT
2009
Springer
14 years 2 months ago
2009
Springer
Testing model transformations requires input models which are graphs of inter-connected objects that must conform to a meta-model and meta-constraints from heterogeneous sources su...
ICST
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract—Software Product Lines (SPL) are difficult to validate due to combinatorics induced by variability across their features. This leads to combinatorial explosion of the n...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...