DATE 1999 - PDF Preprint Papers

DATE 1999 Automation and Test in Europe Conference and Exhibition Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed DATE-1999 Paper

click to vote

DATE
1999
IEEE

194views Hardware» more DATE 1999»

CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems

14 years 4 months ago

Download www.cecs.uci.edu

Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...

Bharat P. Dav

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	194	CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems	claim
2	194	Algorithms for Solving Boolean Satisfiability in Combinational Circuits	claim
3	172	An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems	claim
4	162	MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis	claim
5	147	Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths	claim
6	147	On Analog Signature Analysis	claim
7	147	Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints	claim
8	144	A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester	claim
9	139	OpenJ: An Extensible System Level Design Language	claim
10	138	Codex-dp: Co-design of Communicating Systems Using Dynamic Programming	claim
11	135	Combinational Equivalence Checking Using Satisfiability and Recursive Learning	claim
12	134	Verifying Imprecisely Working Arithmetic Circuits	claim
13	129	Battery-Powered Digital CMOS Design	claim
14	127	Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits	claim
15	123	Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs	claim
16	123	An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length	claim
17	120	Hardware Synthesis from C/C++ Models	claim
18	120	FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy	claim
19	118	Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits	claim
20	115	EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability	claim
21	115	Case Study: System Model of Crane and Embedded Control	claim
22	113	Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems	claim
23	113	Cycle-based Simulation with Decision Diagrams	claim
24	112	Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach	claim
25	112	Fast Hardware-Software Co-simulation Using VHDL Models	claim
26	111	Sequential Circuit Test Generation Using Decision Diagram Models	claim
27	105	Identification and Exploitation of Symmetries in DSP Algorithms	claim
28	102	Minimal Length Diagnostic Tests for Analog Circuits using Test History	claim
29	101	Polynomial Methods for Allocating Complex Components	claim
30	100	The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems	claim
31	95	Object-Oriented Reuse Methodology for VHDL	claim
32	94	An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture	claim
33	92	Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics	claim
34	91	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks	claim
35	89	A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement	claim
36	86	Glitch Power Minimization by Gate Freezing	claim
37	85	At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks	claim
38	82	Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation	claim
39	81	A Power Estimation Model for High-Speed CMOS A/D Converters	claim
40	80	Symmetric Transparent BIST for RAMs	claim
41	80	Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares	claim
42	80	Time Constrained Modulo Scheduling with Global Resource Sharing	claim
43	76	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's	claim
44	74	FSMD Functional Partitioning for Low Power	claim
45	73	Design For Testability Method for CML Digital Circuits	claim
46	73	Channel-Based Behavioral Test Synthesis for Improved Module Reachability	claim
47	72	On Programmable Memory Built-In Self Test Architectures	claim
48	71	Self Recovering Controller and Datapath Codesign	claim
49	66	Specification and Validation of Distributed IP-Based Designs with JavaCAD	claim
50	64	Dynamic Power Management for non-stationary service requests	claim
51	62	Kernel Scheduling in Reconfigurable Computing	claim
52	61	An Efficient Filter-Based Approach for Combinational Verification	claim
53	56	Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers