264 search results - page 22 / 53 » A Time Predictable Instruction Cache for a Java Processor |
OOPSLA
2010
Springer
13 years 7 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
DATE
2011
IEEE
13 years 12 days ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
ISCA
1999
IEEE
14 years 29 days ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
ISCA
2003
IEEE
14 years 1 months ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
IPPS
1998
IEEE
14 years 27 days ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...