264 search results - page 22 / 53 » A Time Predictable Instruction Cache for a Java Processor |
173
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OOPSLA
2010
Springer
15 years 19 days ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
187
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DATE
2011
IEEE
14 years 6 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
ISCA
1999
IEEE
15 years 6 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
141
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ISCA
2003
IEEE
15 years 7 months ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
124
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IPPS
1998
IEEE
15 years 6 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...