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» A Time Predictable Instruction Cache for a Java Processor
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SPAA
2006
ACM
14 years 2 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ACMSE
2004
ACM
14 years 2 months ago
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches....
Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Mi...
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 3 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
CCS
2007
ACM
14 years 2 months ago
Yet another MicroArchitectural Attack: : exploiting I-Cache
Abstract. MicroArchitectural Attacks (MA), which can be considered as a special form of SideChannel Analysis, exploit microarchitectural functionalities of processor implementation...
Onur Aciiçmez
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 1 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...