264 search results - page 46 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ASPLOS
1994
ACM
14 years 21 days ago
1994
ACM
Several researchers have proposed algorithms for basic block reordering. We call these branch alignment algorithms. The primary emphasis of these algorithms has been on improving ...
CASES
2006
ACM
14 years 10 days ago
2006
ACM
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
DFT
2008
IEEE
13 years 10 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
ISCA
1996
IEEE
14 years 23 days ago
1996
IEEE
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
CASES
2006
ACM
14 years 2 months ago
2006
ACM
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions...