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» A Transactional Architecture for Simulation
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IISWC
2009
IEEE
14 years 2 months ago
On the (dis)similarity of transactional memory workloads
— Programming to exploit the resources in a multicore system remains a major obstacle for both computer and software engineers. Transactional memory offers an attractive alternat...
Clay Hughes, James Poe, Amer Qouneh, Tao Li
ISPASS
2010
IEEE
13 years 10 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 8 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
ICDCSW
2007
IEEE
14 years 2 months ago
Transactions in Content-Based Publish/Subscribe Middleware
Content-based publish/subscribe provides a flexible communication model for component interoperation in large-scale environments. In process support systems and other application...
Luis Vargas, Lauri I. W. Pesonen, Ehud Gudes, Jean...
VLDB
1991
ACM
220views Database» more  VLDB 1991»
13 years 11 months ago
A Performance Evaluation of Multi-Level Transaction Management
Multi-level transactions are a variant of open nested transactions in which the subtransactions correspond to operations at different levels of a layered system architecture. The ...
Christof Hasse, Gerhard Weikum