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» A Transactional Architecture for Simulation
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CODES
1997
IEEE
14 years 1 months ago
Optimizing communication in embedded system co-simulation
The Pia hardware-software co-simulator provides substantial speedups over traditional co-simulation methods by permitting dynamic changes in the level of detail when simulating co...
Ken Hines, Gaetano Borriello
ACSAC
1999
IEEE
14 years 1 months ago
Security Architecture Development and Results for a Distributed Modeling and Simulation System
This paper reports on an ongoing effort to define the security architecture for the Joint Simulation System (JSIMS), a joint military modeling and simulation system. It also descr...
Richard B. Neely
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 4 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
WOSP
2005
ACM
14 years 2 months ago
Performance characterization of decentralized algorithms for replica selection in distributed object systems
Designers of distributed systems often rely on replicas for increased robustness, scalability, and performance. Replicated server architectures require some technique to select a ...
Ceryen Tan, Kevin Mills
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 2 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak